(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to reduce a high aspect ratio, for contact holes formed in thick insulator layers.
(2) Description of Prior Art
The use of dynamic random access memory, (DRAM), cells, embedded in a semiconductor chip that is also comprised with peripheral, or non-DRAM, logic devices, has resulted in combinations of thick insulator layers, overlying the peripheral, logic devices. The combination of thick insulator layers, needed to passivate specific DRAM features such as crown shaped capacitor structures, as well as bit line structures, result in difficulties when opening contact holes to active device regions of the peripheral logic devices. The combination of a narrow diameter contact hole, in the thick insulator layers, result in a high aspect ratio contact hole, approaching about 15 to 1, thus presenting difficulties when anisotropically forming the contact holes, as well as presenting difficulties filling the high aspect ratio openings.
This invention will describe a process sequence that allows a narrow diameter contact hole, to be formed in thick insulator layers, without encountering high aspect ratio phenomena. This is accomplished by forming a tee shaped opening, in a lower level of insulator layers, comprised of a wider diameter opening in a top portion of the lower level of insulator layers, and with a narrower diameter opening, formed in the bottom portion of the lower level of insulator layers. When filled with a conductive material, a tee shaped, conductive plug structure is formed, featuring a wider conductive feature, in the wider diameter opening, of the top portion of the lower level insulator layers, overlying the narrower conductive feature, located in the narrow diameter opening, in the lower portion of the lower level of insulator layers. The tee shaped contact hole opening, is accomplished via a dry etch--wet etch procedure, applied to a composite insulator layer, comprised of undoped, and doped, insulator layers. Additional insulator deposition, is followed by the opening of an overlying, second narrow diameter opening, exposing a portion of the top surface of the tee shaped, conductive plug structure. Subsequent metal deposition and patterning is then used to create a conductive plug, in a narrow diameter contact hole, landed on the underlying, wider conductive plug section, of the underlying tee shaped conductive plug structure. The use of this two stage opening, thus reduces the aspect ratio, while the wide metal shape, located in the first narrow diameter opening, allows easier alignment of the second narrow diameter opening to be realized.
Prior art such as Becker et al, in U.S. Pat. No. 5,869,403, describes an opening in a composite insulator layer, comprised of an overlying, thick, doped oxide layer, and an underlying, thin undoped oxide layer, with an undercut in the thin undoped oxide layer. However that prior art features an opening in a composite insulator layer, with the undercut region, located in a thin doped oxide layer. The focus of this present invention, however, not observed in any prior art, is the use of the undercut region, in a contact hole, to allow formation of a tee shaped conductive structure, in a lower contact hole, then overlaid with an upper, narrower conductive plug, located in an upper contact hole, with the upper, narrower conductive plug, landing on the wider, tee shaped region, of the lower conductive plug structure.